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| 50 MHz to 4 GHz TruPwrTM Detector ADL5501 FEATURES True rms response Excellent temperature stability Up to 30 dB input dynamic range at 4 GHz 50 input impedance 1.25 V rms, 15 dBm, maximum input Single-supply operation: 2.7 V to 5.5 V Low power: 3.3 mW at 3 V supply RoHS-compliant 5 1 OUTPUT (V) 0.1 APPLICATIONS Measurement of CDMA2000-, W-CDMA-, and QPSK-/QAMbased OFDM, and other complex modulation waveforms RF transmitter or receiver power measurement -20 -15 -10 -5 0 5 10 15 INPUT (dBm) 06056-001 0.03 -25 Figure 1. Output vs. Input Level, Supply 3 V, Frequency 1.9 GHz GENERAL DESCRIPTION The ADL5501 is a mean-responding power detector for use in high frequency receiver and transmitter signal chains from 50 MHz to 4 GHz. It is easy to apply, requiring only a single supply between 2.7 V and 5.5 V and a power supply decoupling capacitor. The input is internally ac-coupled and has a nominal input impedance of 50 . The output is a linear-responding dc voltage with a conversion gain of 6.3 V/V rms at 900 MHz. The ADL5501 is intended for true power measurement of simple and complex waveforms. The device is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as CDMA-, CDMA2000-, W-CDMA-, and QPSK-/QAMbased OFDM waveforms. The on-chip modulation filter provides adequate averaging for most waveforms. The on-chip, 100 series resistance at the output, combined with an external shunt capacitor, creates a low-pass filter response that reduces the residual ripple in the dc output voltage. For more complex waveforms, an external capacitor at the FLTR pin can be used for supplementary signal demodulation. The ADL5501 offers excellent temperature stability across a 30 dB range and near 0 dB measurement error across temperature over the top portion of the dynamic range. In addition to its temperature stability, the ADL5501 offers low process variations that further reduce calibration complexity. The ADL5501 operates from -40C to +85C and is available in a small 6-lead SC-70 package. It is fabricated on a proprietary high fT silicon bipolar process. FUNCTIONAL BLOCK DIAGRAM ADL5501 RFIN x2 i INTERNAL FILTER CAPACITOR VPOS FLTR TRANSCONDICTANCE CELLS x2 i ERROR AMP BUFFER 100 VRMS COMM Figure 2. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. 06056-002 BAND-GAP REFERENCE ENBL ADL5501 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Circuit Description......................................................................... 16 Filtering........................................................................................ 16 Applications..................................................................................... 17 Basic Connections ...................................................................... 17 Output Swing .............................................................................. 17 Linearity....................................................................................... 17 Input Coupling Using a Series Resistor ................................... 18 Multiple RF Inputs ..................................................................... 18 Selecting the Square-Domain Filter and Output Low-Pass Filter ............................................................................................. 18 Power Consumption, Enable, and Power-On/-Off Response Time ............................................................................................. 19 Output Drive Capability and Buffering................................... 20 VRMS Output Offset ................................................................. 20 Device Calibration and Error Calculation.............................. 21 Calibration for Improved Accuracy......................................... 21 Drift over a Reduced Temperature Range .............................. 22 Operation Below 100 MHz ....................................................... 22 Evaluation Board ........................................................................ 23 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25 REVISION HISTORY 9/06--Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADL5501 SPECIFICATIONS TA = 25C, VS = 3.0 V, CFLTR = Open, COUT = 100 nF, unless otherwise specified. Table 1. Parameter FREQUENCY RANGE RMS CONVERSION (f = 50 MHz) Input Impedance Input Return Loss Dynamic Range 1 1 dB Error 2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept 3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN Input RFIN to Output VRMS Min 50 Typ Max 4000 Unit MHz ||pF dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V/V rms V V V V dB/C dB/C 88||6.5 11.0 CW input, -40C < TA < +85C VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to Output VRMS 25 26 32 35 +8 -18 4.5 0.03 1.81 0.11 0.0039 -0.0037 79||3.6 12.4 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept VS = 5 V VS = 5 V PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C 28 19 20 23 27 26 30 +6 -18 6.1 5.6 0.03 -0.02 2.47 0.13 0.0028 -0.0018 +0.1 7.8 RMS CONVERSION (f = 100 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error 4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. 0 | Page 3 of 28 ADL5501 Parameter RMS CONVERSION (f = 450 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to Output VRMS Min Typ 65||1.4 15.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to Output VRMS 32 20 24 25 29 28 33 +5 -20 7.1 0.03 2.81 0.15 0.0016 -0.0002 55||0.9 17 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA +85C -40C TA +25C 33 20 23 24 27 27 30 +6 -18 6.3 0.03 2.53 0.14 0.0019 -0.0002 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C RMS CONVERSION (f = 900 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. 0 | Page 4 of 28 ADL5501 Parameter RMS CONVERSION (f = 1900 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to Output VRMS Min Typ 36||0.4 14.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to Output VRMS 32 5 7 25 29 28 32 +7 -19 5.5 0.02 2.20 0.12 0.0031 -0.0034 32||0.3 13.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C 8 4 7 25 29 29 32 +8 -18 5.0 0.02 2.00 0.10 0.0032 -0.0044 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C RMS CONVERSION (f = 2350 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Rev. 0 | Page 5 of 28 ADL5501 Parameter RMS CONVERSION (f = 2700 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity Condition Input RFIN to Output VRMS Min Typ 31||-0.1 12.5 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C Input RFIN to Output VRMS 5 3 7 25 30 28 33 +8 -17 4.6 0.02 1.84 0.09 0.0034 -0.0049 36||-0.4 11.8 CW input, -40C < TA < +85C Delta from 25C, VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V VS = 3 V VS = 5 V 1 dB error2 1 dB error2 VOUT = (Gain x VIN) + Intercept PIN = 5 dBm, 400 mV rms PIN = -21 dBm, +20 mV rms PIN = -5 dBm 25C TA 85C -40C TA +25C No signal at RFIN Pin ENBL 2.7 V VS 5.5 V, -40C < TA < +85C 2.7 V at ENBL, -40C TA +85C 2.7 V VS 5.5 V, -40C < TA < +85C CFLTR = COUT = Open, 0 dBm at RFIN CFLTR = 1 nF, COUT = Open, 0 dBm at RFIN CFLTR = Open, COUT = 100 nF, 0 dBm at RFIN 5 4 5 28 31 30 33 +10 -18 3.8 0.01 1.53 0.07 0.0019 -0.0043 50 1.8 0.05 -0.5 6 21 28 150 VPOS 0.1 +0.5 Max Unit ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF dB dB dB dB dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C mV V A V s s s RMS CONVERSION (f = 4000 MHz) Input Impedance Input Return Loss Dynamic Range1 0.25 dB Error4 0.25 dB Error2 1 dB Error2 2 dB Error2 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept3 Output Voltage--High Power In Output Voltage--Low Power In Temperature Sensitivity OUTPUT OFFSET ENABLE INTERFACE Logic Level to Enable Power, HI Condition Input Current when HI Logic Level to Disable Power, LO Condition Power-Up Response Time 5 Rev. 0 | Page 6 of 28 ADL5501 Parameter POWER SUPPLIES Operating Range Quiescent Current Total Supply Current When Disabled 1 2 3 Condition -40C < TA < +85C No signal at RFIN 6 No signal at RFIN, ENBL Input LO Min 2.7 Typ Max 5.5 Unit V mA A 1.1 0.1 <10 The available output swing, and hence, the dynamic range, is altered by the supply voltage; see Figure 8. Error referred to best-fit line at 25C. Calculated using linear regression. 4 Error referred to delta from 25C response; see Figure 13, Figure 14, Figure 15, Figure 19, Figure 20, and Figure 21. 5 The response time is measured from 10% to 90% of settling level; see Figure 30. 6 Supply current is input-level dependent; see Figure 6. Rev. 0 | Page 7 of 28 ADL5501 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VS VRMS RFIN Equivalent Power, re 50 Internal Power Dissipation JA (SC-70) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V, VS 1.25 V rms 15 dBm 80 mW 494C/W 125C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 8 of 28 ADL5501 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPOS FLTR RFIN 1 6 VRMS ENBL COMM 06056-003 2 ADL5501 TOP VIEW (Not to Scale) 5 3 4 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 Mnemonic VPOS FLTR Description Supply Voltage Pin. Operational range 2.7 V to 5.5 V. Square-Domain Filter Pin. Connection for an external capacitor to lower the corner frequency of the squaredomain (or modulation) filter. Capacitor is connected between FLTR and VS and forms a low-pass filter with an 8 k on-chip resistor. The on-chip capacitor provides filtering with an approximate 100 kHz corner frequency. For simple waveforms, no further filtering of the demodulated signal is required. Signal Input Pin. Internally ac-coupled after internal termination resistance. Nominal 50 input impedance. Device Ground Pin. Enable Pin. Connect pin to VS for normal operation. Connect pin to ground for disable mode for a supply current less than 1 A. Output Pin. Rail-to-rail voltage output with limited 3 mA current drive capability. The output has an internal 100 series resistance. High resistive loads are recommended to preserve output swing. 3 4 5 6 RFIN COMM ENBL VRMS Rev. 0 | Page 9 of 28 ADL5501 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VS = 5.0 V, CFLTR = open, COUT = 100 nF, Colors: black = +25C, blue = -40C, red = +85C, unless otherwise noted. 10 3 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 4000MHz 2 1 ERROR (dB) 06056-004 OUTPUT (V) 1 0 0.1 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 4. Output vs. Input Level; Frequencies100 MHz, 450 MHz, 900 MHz,1900 MHz, 2350 MHz, 2700 MHz, and 4000 MHz; Supply 5.0 V 5.0 4.5 4.0 3.5 Figure 7. Linearity Error vs. Input Level; Frequencies 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 4000 MHz; Supply 5.0 V 10 5.5V 5.0V 3.0V 2.7V OUTPUT (V) 2.5 2.0 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 4000MHz 06056-005 OUTPUT (V) 3.0 1 0.1 1.2 1.4 -20 -15 -10 -5 0 5 10 15 INPUT (V rms) INPUT (dBm) Figure 5. Output vs. Input Level (Linear Scale); Frequencies 100 MHz, 450 MHz, 900 MHz, 1900 MHz, 2350 MHz, 2700 MHz, and 4000 MHz; Supply 5.0 V 12 11 10 Figure 8. Output vs. Input Level; Supply 2.7 V, 3.0 V, 5.0 V, and 5.5 V; Frequency 900 MHz 18 16 5.0V 3.0V RETURN LOSS (dB) SUPPLY CURRENT (mA) 9 8 7 6 5 4 3 2 1 14 12 10 06056-006 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 1 2 FREQUENCY (GHz) 3 4 INPUT (V rms) Figure 6. Supply Current vs. Input Level; Supplies 3.0 V and 5.0 V; Temperatures -40C, +25C, and +85C Figure 9. Return Loss vs. Frequency Rev. 0 | Page 10 of 28 06056-009 0 8 06056-008 0.03 -25 06056-007 0.03 -25 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 4000MHz -1 -2 -3 -25 ADL5501 3 3 2 2 1 ERROR (dB) ERROR (dB) 06056-010 1 0 0 -1 -1 -2 -2 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 10. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 900 MHz; Supply 5.0 V 3 Figure 13. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 900 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 06056-011 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 11. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 1900 MHz; Supply 5.0 V 3 Figure 14. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 1900 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 06056-012 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 12. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 2350 MHz; Supply 5.0 V Figure 15. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 2350 MHz, Supply 5.0 V Rev. 0 | Page 11 of 28 06056-015 -3 -25 -3 -25 06056-014 -3 -25 -3 -25 06056-013 -3 -25 -3 -25 ADL5501 3 3 2 2 1 ERROR (dB) ERROR (dB) 06056-016 1 0 0 -1 -1 -2 -2 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 16. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 2700 MHz; Supply 5.0 V 3 Figure 19. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 2700 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 06056-017 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 17. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 3500 MHz; Supply 5.0 V 3 Figure 20. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 3500 MHz, Supply 5.0 V 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -1 -2 -2 06056-018 -20 -15 -10 -5 0 5 10 15 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) INPUT (dBm) Figure 18. Temperature Drift Distributions for 50 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 4000 MHz; Supply 5.0 V Figure 21. Output Delta from 25C Output Voltage for 50 Devices at -40C and +85C, Frequency 4000 MHz, Supply 5.0 V Rev. 0 | Page 12 of 28 06056-021 -3 -25 -3 -25 06056-020 -3 -25 -3 -25 06056-019 -3 -25 -3 -25 ADL5501 5 3 CW QPSK, 4.8dB CF 2 1 ERROR (dB) VOUT (V) 8PSK, 4.8dB CF 16QAM, 6.3dB CF 64QAM, 7.4dB CF 1 0 0.1 CW QPSK 8PSK 16QAM 64QAM 06056-022 -1 -2 -20 -15 -10 -5 0 5 10 -20 -15 -10 -5 0 5 10 INPUT (dBm) INPUT (dBm) Figure 22. Output vs. Input Level with Different Waveforms, 10 MHz Signal BW for All Modulated Signals, Supply 5.0 V, Frequency 1900 MHz 3 Figure 25. Error from CW Linear Reference vs. Input with Different Waveforms, 10 MHz Signal BW for All Modulated Signals, Supply 5.0 V, Frequency 1900 MHz 3 2 2 1 ERROR (dB) ERROR (dB) 1 0 0 -1 -2 CW BPSK, 11dB CF QPSK, 11dB CF 16QAM, 12dB CF 64QAM, 11dB CF 06056-023 -1 -2 CW BPSK, 11dB CF QPSK, 11dB CF 16QAM, 12dB CF 64QAM, 11dB CF -20 -15 -10 -5 0 5 10 06056-026 06056-027 -3 -25 -20 -15 -10 -5 0 5 10 -3 -25 RFIN (dBm) RFIN (dBm) Figure 23. Error from CW Linear Reference vs. Input Level for Various 802.16 OFDM Waveforms at 2.35 GHz, 10 MHz Signal BW, and 256 Subcarriers for All Modulated Signals, Supply 5.0 V 3 CW 12.2kbps, DPCCH (-5.46dB, 15kSPS) + DPDCH (0dB, 60kSPS), 3.4dB CF 64kbps, DPCCH (-9.54dB, 15kSPS) + DPDCH (0dB, 240kSPS), 3.4dB CF 144kbps, DPCCH (-11.48dB, 15kSPS) + DPDCH (0dB, 480kSPS), 3.3dB CF 384kbps, DPCCH (-11.48dB, 15kSPS) + DPDCH (0dB, 960kSPS), 3.3dB CF 768kbps, DPCCH (-11.48dB, 15kSPS) + DPDCH1 + 2 (0dB, 960kSPS), 5.8dB CF Figure 26. Error from CW Linear Reference vs. Input Level for Various 802.16 OFDM Waveforms at 3.5 GHz, 10 MHz Signal BW, and 256 Subcarriers for All Modulated Signals, Supply 5.0 V 3 CW PICH, 4.7dB CF PICH + FCH (9.6kbps), 4.8dB CF PICH + FCH (9.6kbps) + DCCH, 6.3dB CF PICH + FCH (9.6kbps) + SCH (153.6kbps), 6.7dB CF PICH + FCH (9.6kbps) + DCCH + SCH (153.6kbps), 7.6dB CF 2 2 1 ERROR (dB) 1 ERROR (dB) 0 0 -1 -1 -2 -2 -20 -15 -10 -5 0 5 10 06056-024 -3 -25 -3 -25 -20 -15 -10 -5 0 5 10 RFIN (dBm) RFIN (dBm) Figure 24. Error from CW Linear Reference vs. Input with Various W-CDMA Up Link Waveforms at 1900 MHz, CFLTR = Open, COUT = 100 nF Figure 27. Error from CW Linear Reference vs. Input with Various CDMA2000 Reverse Link Waveforms at 900 MHz, CFLTR = 1 nF, COUT = 100 nF Rev. 0 | Page 13 of 28 06056-025 0.03 -25 -3 -25 ADL5501 3 CW TEST MODEL TEST MODEL TEST MODEL TEST MODEL TEST MODEL TEST MODEL 3 1 w/ 1 w/ 1 w/ 1 w/ 1 w/ 1 w/ 16 DPCH, 32 DPCH, 64 DPCH, 64 DPCH, 64 DPCH, 64 DPCH, 1 CARRIER 1 CARRIER 1 CARRIER 2 CARRIERS 3 CARRIERS 4 CARRIERS 2 2 CW SR1, SR1, SR1, SR1, PILOT CHANNEL, 1 CARRIER 9 CHANNEL, 1 CARRIER 9 CHANNEL, 3 CARRIERS 9 CHANNEL, 4 CARRIERS 1 ERROR (dB) 1 ERROR (dB) 0 0 -1 -1 -2 -2 -20 -15 -10 -5 0 5 10 -20 -15 -10 -5 0 5 10 RFIN (dBm) INPUT (dBm) Figure 28. Error from CW Linear Reference vs. Input with Various WCDMA Down Link Waveforms at 2140 MHz, CFLTR = 1 nF, COUT = 100 nF Figure 31. Error from CW Linear Reference vs. Input with Various CDMA2000 Fwd Link Waveforms at 2140 MHz, CFLTR = 1 nF, COUT = 100 nF PULSED RFIN OSCILLOSCOPE ADL5501 VPOS FLTR RFIN VRMS ENBL COMM 6 FET PROBE POWER SUPPLY CFLTR VRMS (500mV/DIV) C1 100pF C2 0.1F 1 400mV rms RF INPUT 250mV rms 160mV rms COUT 2 5 ROUT 06056-029 RF PULSE GENERATOR 3 4 70mV rms 40s/DIV Figure 29. Hardware Configuration for Output Response to RF Input Pulse Figure 32. Output Response to Various RF Input Pulse Levels, Supply 3 V, Frequency 900 MHz, CFLTR = 1 nF, COUT = Open, ROUT = Open PULSED RFIN PULSED RFIN VRMS (500mV/DIV) 400mV rms RF INPUT VRMS (500mV/DIV) 400mV rms RF INPUT 250mV rms 160mV rms 250mV rms 160mV rms 70mV rms 70mV rms 06056-030 40s/DIV 100s/DIV Figure 30. Output Response to Various RF Input Pulse Levels, Supply 3 V, Frequency 900 MHz, CFLTR = Open, COUT = Open, ROUT = Open Figure 33. Output Response to Various RF Input Pulse Levels, Supply 3 V, Frequency 900 MHz, CFLTR = Open, COUT = 0.1 F, ROUT = 1 k Rev. 0 | Page 14 of 28 06056-033 06056-032 06056-031 06056-028 -3 -25 -3 -25 ADL5501 OSCILLOSCOPE C1 100pF POWER SUPPLY CFLTR 2 ENBL C2 0.1F 1 ADL5501 VPOS FLTR RFIN VRMS ENBL COMM 6 FET PROBE VRMS (500mV/DIV) 400mV rms RF INPUT COUT 5 ROUT 250mV rms 160mV rms RF SIGNAL GENERATOR 3 4 PULSE GENERATOR AD811 06056-034 70mV rms 50 732 40s/DIV Figure 34. Hardware Configuration for Output Response to Enable Gating Measurements ENBL Figure 37. Output Response to Enable Gating at Various RF Input Levels, Supply 3 V, Frequency 900 MHz, CFLTR = 1 nF, COUT = Open, ROUT = Open ENBL 400mV rms RF INPUT VRMS (500mV/DIV) 400mV rms RF INPUT VRMS (500mV/DIV) 250mV rms 160mV rms 250mV rms 160mV rms 70mV rms 70mV rms 06056-035 40s/DIV 100s/DIV Figure 35. Output Response to Enable Gating at Various RF Input Levels, Supply 3 V, Frequency 900 MHz, CFLTR = Open, COUT = Open, ROUT = Open 8 Figure 38. Output Response to Enable Gating at Various RF Input Levels, Supply 3 V, Frequency 900 MHz, CFLTR = Open, COUT = 0.1 F, ROUT = 1 k 100 7 CONVERSION GAIN (V/V rms) 80 INTERCEPT (mV) 6 60 5 40 4 20 3 0 06056-036 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. Conversion Gain vs. Frequency, Supply 5 V Figure 39. Intercept vs. Frequency, Supply 5 V Rev. 0 | Page 15 of 28 06056-039 2 -20 06056-038 06056-037 ADL5501 CIRCUIT DESCRIPTION The ADL5501 is an rms-responding (mean power) detector that provides an approach to the exact measurement of RF power that is independent of waveform. It achieves this function by using a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high gain error amplifier. The signal to be measured is applied to the input of the first squaring cell through the input matching network. The input is matched to offer a broadband 50 input impedance from 50 MHz to 4 GHz. The input matching network has a high-pass corner frequency of approximately 70 MHz. The ADL5501 responds to the voltage, VIN, at its input by squaring this voltage to generate a current proportional to VIN2. This current is applied to an internal load resistor in parallel with a capacitor, followed by a low-pass filter, which extracts the mean of VIN2. Although essentially voltage responding, the associated input impedance calibrates this port in terms of equivalent power. Therefore, 1 mW corresponds to a voltage input of 224 mV rms referenced to 50 . Because both the squaring cell input impedance and the input matching network are frequency dependent, the conversion gain is a function of signal frequency. The voltage across the low-pass filter, whose frequency can be arbitrarily low, is applied to one input of an error-sensing amplifier. A second identical voltage-squaring cell is used to close a negative feedback loop around this error amplifier. This second cell is driven by a fraction of the quasi-dc output voltage of the ADL5501. When the voltage at the input of the second squaring cell is equal to the rms value of VIN, the loop is in a stable state, and the output then represents the rms value of the input. By completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several benefits arise. First, scaling effects in these cells cancel; therefore, the overall calibration can be accurate, even though the open-loop response of the squaring cells taken separately need not be. Note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scaling. Second, the tracking in the responses of the dual cells remains very close over temperature, leading to excellent stability of calibration. The squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. However, the dynamic range of such a system is small, due in part to the much larger dynamic range at the output of the squaring cells. There are practical limitations to the accuracy of sensing very small error signals at the bottom end of the dynamic range, arising from small random offsets that limit the attainable accuracy at small inputs. On the other hand, the squaring cells in the ADL5501 have a Class AB aspect; the peak input is not limited by its quiescent bias condition but is determined mainly by the eventual loss of square-law conformance. Consequently, the top end of their response range occurs at a large input level (approximately 700 mV rms), while preserving a reasonably accurate square-law response. The maximum usable range is, in practice, limited by the output swing. The rail-to-rail output stage can swing from a few millivolts above ground to within 100 mV below the supply. An example of the output induced limit, given a conversion gain of 6.3 V/V rms at 900 MHz and assuming a maximum output of 2.9 V with a 3 V supply, has a maximum input of 2.9 V rms/6.3 or 460 mV rms. FILTERING An important aspect of rms-dc conversion is the need for averaging (the function is root-mean-square). The on-chip averaging in the square domain has a corner frequency of approximately 100 kHz and is sufficient for common modulation signals, such as CDMA-, WCDMA-, and QPSK-/QAMbased OFDM (for example, WLAN and WiMAX). For more complex RF waveforms (with modulation components extending down into the kilohertz region), more filtering is necessary to supplement the on-chip, low-pass filter. For this reason, the FLTR pin is provided; a capacitor attached between this pin and VPOS can extend the averaging time to very low frequencies. Adequate filtering ensures the accuracy of the rms measurement; however, some ripple or ac residual can still be present on the dc output. To reduce this ripple, an external shunt capacitor can be used at the output to form a low-pass filter with the on-chip, 100 resistance (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section). Rev. 0 | Page 16 of 28 ADL5501 APPLICATIONS BASIC CONNECTIONS Figure 40 shows the basic connections for the ADL5501. The device is powered by a single supply of between 2.7 V and 5.5 V, with a quiescent current of 1.1 mA. The VPOS pin is decoupled using 100 pF and 0.1 F capacitors. The ADL5501 RF input does not require external termination components because it is internally matched for an overall broadband input impedance of 50 . +VS 2.7V TO 5.5V 100pF 0.1F 1 LINEARITY Because the ADL5501 is a linear-responding device, plots of output voltage vs. input voltage result in a straight line. It is more useful to plot the error on a logarithmic scale, as shown in Figure 42. The deviation of the plot for the ideal straight-line characteristic is caused by output clipping at the high end and by signal offsets at the low end. However, it should be noted that offsets at the low end can be either positive or negative; therefore, this plot could also trend upwards at the low end. Figure 10 through Figure 12 and Figure 16 through Figure 18 show error distributions for a large population of devices at specific frequencies. 3 100MHz 450MHz 900MHz 1900MHz 2350MHz 2700MHz 4000MHz ADL5501 VPOS FLTR RFIN VRMS ENBL COMM 6 VRMS COUT CFLTR 2 5 2 06056-040 RFIN 3 4 1 ERROR (dB) Figure 40. Basic Connections for ADL5501 OUTPUT SWING At 900 MHz, the output voltage is nominally 6.3 times the input rms voltage (a conversion gain of 6.3 V/V rms). The output voltage swings from near ground to 4.9 V on a 5.0 V supply. Figure 41 shows the output swing of the ADL5501 to a CW input for various supply voltages. It is clear from Figure 41 that operating the device at lower supply voltages reduces the dynamic range as the output headroom decreases. 10 5.5V 5.0V 0 -1 -2 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 42. Representative Unit, Error in dB vs. Input Level, VS = 5.0 V 3.0V 2.7V OUTPUT (V) 1 It is also apparent in Figure 42 that the error plot tends to shift to the right with increasing frequency. The squaring cell has an input impedance that decreases with frequency. The matching network compensates for the change and maintains the input impedance at a nominal 50 . The result is a decrease in the actual voltage across the squaring cell as the frequency increases, reducing the conversion gain. Similarly, conversion gain is less at frequencies near 100 MHz because of the small on-chip coupling capacitor. 0.1 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 41. Output Swing for Supply Voltages of 2.7 V, 3.0 V, 5.0 V, and 5.5 V 06056-041 0.03 -25 Rev. 0 | Page 17 of 28 06056-042 -3 -25 ADL5501 INPUT COUPLING USING A SERIES RESISTOR Figure 43 shows a technique for coupling the input signal into the ADL5501 that can be applicable where the input signal is much larger than the input range of the ADL5501. A series resistor combines with the input impedance of the ADL5501 to attenuate the input signal. Because this series resistor forms a divider with the frequency dependent input impedance, the apparent gain changes greatly with frequency. However, this method has the advantage of very little power being tapped off in RF power transmission applications. If the resistor is large compared to the transmission line's impedance, the VSWR of the system is relatively unaffected. RSERIES BAND 1 DIRECTIONAL COUPLER 50 BAND 2 DIRECTIONAL COUPLER 50 16.5 16.5 RFIN ADL5501 Figure 44. Combining Multiple RF Input Signals SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER The internal filter capacitor of the ADL5501 provides averaging in the square domain but leaves some residual ac on the output. Signals with high peak-to-average ratios, such as W-CDMA or CDMA2000, can produce ac-residual levels on the ADL5501 dc output. To reduce the effects of these low frequency components in the waveforms, some additional filtering is required. RFIN RFIN ADL5501 Figure 43. Attenuating the Input Signal The resistive tap or series resistance, RSERIES, can expressed as RSERIES = RIN (1 - 10ATTN/20)/(10ATTN/20) where: RIN is the input impedance of RFIN. ATTN is the desired attenuation factor in dB. For example, if a power amplifier with a maximum output power of +28 dBm is matched to the ADL5501 input at +5 dBm, then a -23 dB attenuation factor is required. At 900 MHz, the input resistance, RIN, is 55 . RSERIES = (55 )(1 - 10-23/20)/(10-23/20) = 722 Thus, for an attenuation of -23 dB, a series resistance of approximately 722 is needed. (2) (1) 06056-043 The square-domain filter capacitance of the ADL5501 can be augmented by connecting a capacitor between Pin 2 (FLTR) and Pin 1 (VPOS). In addition, the output of the ADL5501 can be filtered directly by placing a capacitor between VRMS (Pin 6) and ground. The combination of the on-chip, 100 output series resistance and the external shunt capacitor forms a lowpass filter to reduce the residual ac. Table 4 shows the effect of several capacitor values for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. Note that large load capacitances increase the turn-on and pulse response times (see Figure 30, Figure 32, Figure 33, Figure 35, Figure 37, and Figure 38). For more information on the effects of the filter capacitances on the response, see the Power Consumption, Enable, and Power-On/-Off Response Time section. MULTIPLE RF INPUTS Figure 44 shows a technique for combining multiple RF input signals to the ADL5501. Some applications can share a single detector for multiple bands. Three 16.5 resistors in a T-network combine the three 50 terminations (including the ADL5501). The broadband resistive combiner ensures each port of the T-network sees a 50 termination. Because there are only 6 dB of isolation from one port of the combiner to the other ports, only one band should be active at a time. Rev. 0 | Page 18 of 28 06056-044 16.5 ADL5501 Table 4. Waveform and Output Filter Effects on Residual AC Waveform 64QAM (7.4 dB CF) CFILT, COUT 1 nF, Open Open, 0.1 F 1 nF, 0.1 F W-CDMA RL (3.4 dB CF) 1 nF, Open Open, 0.1 F 1 nF, 0.1 F CDMA2000 DL (6.7 dB CF) 1 nF, Open Open, 0.1 F 1 nF, 0.1 F W-CDMA UL TM1-64, 1 CR 1 nF, Open Open, 0.1 F 1 nF, 0.1 F Output V dc 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 Residual AC mV p-p mV rms 83 11 175 21 394 47 49 5.5 98 11 212 23 45 5.5 93 11 200 24 6.4 0.8 19 2.6 52 6.6 4.5 0.6 16 2.2 36 4.9 3.1 0.5 9.6 1.4 27 3.9 67 8.6 148 19 339 43 28 3.9 56 7.9 119 17 26 3.7 52 7.7 116 17 204 32 396 64 840 140 60 11 112 21 227 42 56 11 114 21 243 45 If the input of the ADL5501 is driven while the device is disabled (ENBL = COMM), the leakage current of less than 1 A increases as a function of input level. When the device is disabled, the output impedance increases to approximately 33.5 k. The turn-on time and pulse response is strongly influenced by the size of the square-domain filter and output shunt capacitor. Figure 45 shows a plot of the output response to an RF pulse on the RFIN pin, with a 0.1 F output filter capacitor and no square-domain filter capacitor. The falling edge is particularly dependent on the output shunt capacitance, as shown in Figure 45. PULSED RFIN 400mV rms RF INPUT VRMS (500mV/DIV) 250mV rms 160mV rms 70mV rms 2ms/DIV Figure 45. Output Response to Various RF Input Pulse Levels, Supply 3 V, Frequency 900 MHz, Square-Domain Filter Open, Output Filter 0.1 F To improve the falling edge of the enable and pulse responses, a resistor can be placed in parallel with the output shunt capacitor. The added resistance helps to discharge the output filter capacitor. Although this method reduces the power-off time, the added load resistor also attenuates the output (see the Output Drive Capability and Buffering section). PULSED RFIN 400mV rms RF INPUT VRMS (500mV/DIV) 250mV rms 160mV rms 70mV rms POWER CONSUMPTION, ENABLE, AND POWERON/-OFF RESPONSE TIME The quiescent current consumption of the ADL5501 varies with the size of the input signal from approximately 1.1 mA for no signal up to 6.2 mA at an input level of 0.7 V rms (10 dBm, re 50 ). If the input is driven beyond this point, the supply current increases sharply (as shown in Figure 6). There is little variation in quiescent current with power supply voltage. The ADL5501 can be disabled either by pulling the ENBL (Pin 5) to COMM (Pin 4) or by removing the supply power to the device. Disabling the device via the ENBL function reduces the leakage current to less than 1 A. 2ms/DIV Figure 46. Output Response to Various RF Input Pulse Levels, Supply 3 V, Frequency 900 MHz, Square-Domain Filter Open, Output Filter 0.1 F with Parallel 1 k The square-domain filter improves the rms accuracy for high crest factors (see the Selecting the Square-Domain Filter and Output Low-Pass Filter), but it can hinder the response time. For optimum response time and low ac residual, both the square-domain filter and the output filter should be used. Rev. 0 | Page 19 of 28 06056-046 06056-045 ADL5501 The square-domain filter at FLTR can be reduced to improve response time, and the remaining ac residual can be decreased by using the output filter, which has a smaller time constant. 5V 0.1F 100pF OUTPUT DRIVE CAPABILITY AND BUFFERING The ADL5501 is capable of sourcing an output current of approximately 3 mA. The output current is sourced through the on-chip, 100 series resistor; therefore, any load resistor forms a voltage divider with this on-chip resistance. It is recommended that the ADL5501 drive high resistive loads to preserve output swing. If an application requires driving a low resistance load, a simple buffering circuit can be used, as shown in Figure 49. Similar circuits can be used to increase or decrease the nominal conversion gain (see Figure 47 and Figure 48). In Figure 48, the AD8031 buffers a resistive divider to give half of the slope. In Figure 47, the op amp gain of two doubles the slope. Using other resistor values, the slope can be changed to an arbitrary value. The AD8031 rail-to-rail op amp, used in these examples, can swing from 50 mV to 4.95 V on a single 5 V supply and operates at supply voltages down to 2.7 V. If high output current is required (>10 mA), the AD8051, which also has rail-to-rail capability, can be used down to a supply voltage of 3 V. It can deliver up to 45 mA of output current. 5V 0.1F 100pF VPOS VRMS 0.01F ADL5501 COMM AD8031 6.3V/V rms Figure 49. Output Buffering Options, Slope of 6.3 V/V rms at 900 MHz VRMS OUTPUT OFFSET The ADL5501 has a 1 dB error detection range of about 30 dB, as shown in Figure 10 to Figure 12 and Figure 16 to Figure 18. The error is referred to the best-fit line defined in the linear region of the output response. Below an input power of -20 dBm, the response is no longer linear and begins to lose accuracy. In addition, depending on the supply voltage, saturation of the output limits the detection accuracy above 10 dBm. Calibration points should be chosen in the linear region, avoiding the nonlinear ranges at the high and low extremes. 10 1 OUTPUT (V) VPOS VRMS 0.01F ADL5501 COMM AD8031 12.6V/V rms 0.1 5k 5k 06056-047 06056-050 0.01 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 Figure 47. Output Buffering Options, Slope of 12.6 V/V rms at 900 MHz 5V 0.1F 100pF INPUT (dBm) Figure 50. Output vs. Input Level Distribution of 50 Devices, Frequency 900 MHz, Supply 5.0 V VPOS VRMS 4k 5k 0.01F ADL5501 COMM AD8031 3.2V/V rms 06056-048 Figure 48. Output Buffering Options, Slope of 3.2 V/V rms at 900 MHz Figure 50 shows the distribution of the output response vs. the input power for multiple devices. The ADL5501 loses accuracy at low input powers as the output response begins to fan out. As the input power is reduced, the spread of the output response increases along with the error. Although some devices follow the ideal linear response at very low input powers, not all devices continue the ideal linear regression to a near 0 V y-intercept. Some devices exhibit output responses that rapidly decrease, and some flatten out. With no RF signal applied, the ADL5501 has a typical output offset of 50 mV (with a maximum of 150 mV). Rev. 0 | Page 20 of 28 06056-049 ADL5501 DEVICE CALIBRATION AND ERROR CALCULATION Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. In general, calibration is performed by applying two input power levels to the ADL5501 and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear operating range of the device. The best-fit line is characterized by calculating the conversion gain (or slope) and intercept using the following equations: Gain = (VRMS2 - VRMS1)/(VIN2 - VIN1) Intercept = VRMS1 - (Gain x VIN1) where: VIN is the rms input voltage to RFIN. VRMS is the voltage output at VRMS. Once gain and intercept are calculated, an equation can be written that allows calculation of an (unknown) input power based on the measured output voltage. VIN = (VRMS - Intercept)/Gain (5) For an ideal (known) input power, the law conformance error of the measured data can be calculated as ERROR (dB) = 20 x log [(VRMS, MEASURED - Intercept)/(Gain x VIN, IDEAL)] (6) Figure 51 includes a plot of the error at 25C, the temperature at which the ADL5501 is calibrated. Note that the error is not zero. This is because the ADL5501 does not perfectly follow the ideal linear equation, even within its operating region. The error at the calibration points is, however, equal to 0 by definition. 3 CALIBRATION FOR IMPROVED ACCURACY Another way of presenting the error function of the ADL5501 is shown in Figure 52. In this case, the dB error at hot and cold temperatures is calculated with respect to the transfer function at ambient. This is a key difference in comparison to the previous plots. Up to now, the errors were calculated with respect to the ideal linear transfer function at ambient. When this alternative technique is used, the error at ambient becomes equal to 0 by definition (see Figure 52). This plot is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) response at ambient. The linearity and dynamic range tend to be improved artificially with this type of plot because the ADL5501 does not perfectly follow the ideal linear equation (especially outside of its linear operating range). Achieving this level of accuracy in an end application requires calibration at multiple points in the operating range of the device. In some applications, very high accuracy is required at just one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. The ADL5501 offers a tight error distribution in the high input power range, as shown in Figure 52. The high accuracy range, centered around 9 dBm at 1900 MHz, offers 7 dB of 0.1 dB detection error over temperature. Multiple point calibration at ambient temperature in the reduced range offers precise power measurement with near 0 dB error from -40C to +85C. 3 (3) (4) 2 ERROR (dB) 2 1 +85C +25C 1 ERROR (dB) +85C +25C 0 -40C 0 -40C -1 -1 -2 -2 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) -20 -15 -10 -5 0 5 10 15 06056-051 -3 -25 Figure 52. Error from +25C Output Voltage at -40C, +25C, and +85C After Ambient Normalization, Frequency 1900 MHz, Supply 5.0 V INPUT (dBm) Figure 51. Error from Linear Reference vs. Input at -40C, +25C, and +85C vs. +25C Linear Reference, Frequency 1900 MHz, Supply 5.0 V Figure 51 also includes error plots for the output voltage at -40C and +85C. These error plots are calculated using the gain and intercept at 25C. This is consistent with calibration in a mass-production environment where calibration at temperature is not practical. The high accuracy range center varies over frequency. At 1900 MHz, the region is centered at approximately 9 dBm. At higher frequencies, the high accuracy range is centered at higher input powers (see Figure 13 through Figure 15 and Figure 19 through Figure 21). Rev. 0 | Page 21 of 28 06056-052 -3 -25 ADL5501 DRIFT OVER A REDUCED TEMPERATURE RANGE Figure 53 shows the error over temperature for a 1.9 GHz input signal. Error due to drift over temperature consistently remains within 0.25 dB and only begins to exceed this limit when the ambient temperature goes above +25C and below -10C. For all frequencies using a reduced temperature range, higher measurement accuracy is achievable. 1.00 0.75 0.50 ERROR (dB) 3 2 1 ERROR (dB) 0 +85C +70C +50C +35C +25C +15C 0C -10C -25C -40C -1 -2 -20 -15 -10 -5 0 5 10 15 0 -0.25 -0.50 -0.75 -1.00 -25 INPUT (dBm) Figure 55. Output Delta from +25C Output Voltage for 12 Devices at -40C and +85C, Frequency 50 MHz, Supply 5.0 V OPERATION BELOW 100 MHZ The ADL5501 works at frequencies below 100 MHz, but exhibits slightly higher linearity error. Figure 54 shows the error distribution of 12 devices at 50 MHz over temperature. When compared to an ideal linear transfer function at ambient, the error of the ADL5501 over temperature remains within 0.5 dB for the central 20 dB of the dynamic range. At the higher input power levels, the error grows as the response becomes nonlinear. Due to the repeatability of the performance from part to part, compensation can be applied to reduce the effects of temperature drift and linearity error. To detect larger dynamic ranges at lower frequencies, the transfer function at ambient can be calibrated, thus eliminating the linearity error. This technique is discussed in detail in the Calibration for Improved Accuracy section. Figure 55 shows that the dynamic range within 0.5 dB error improves to 30 dB by using this method. -20 -15 -10 -5 0 5 10 15 INPUT (dBm rms) Figure 53. Typical Drift at 1.9 GHz for Various Temperatures 3 2 1 ERROR (dB) 0 -1 -2 -20 -15 -10 -5 0 5 10 15 INPUT (dBm) Figure 54. Temperature Drift Distributions for 12 Devices at -40C, +25C, and +85C vs. +25C Linear Reference; Frequency 50 MHz; Supply 5.0 V 06056-053 -3 -25 06056-100 Rev. 0 | Page 22 of 28 06056-054 0.25 -3 -25 ADL5501 EVALUATION BOARD Figure 56 shows the schematic of the ADL5501 evaluation board. The layout and silkscreen of the evaluation board layers are shown in Figure 57 to Figure 60. The board is powered by a single supply in the 2.7 V to 5.5 V range. The power supply is decoupled by 100 pF and 0.1 F capacitors. Table 5 details the various configuration options of the evaluation board. Problems caused by impedance mismatch can arise using the evaluation board to examine the ADL5501 performance. One way to reduce these problems is to put a coaxial 3 dB attenuator on the RFIN SMA connector. Mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board, can cause these problems. A simple (and common) example of such a problem is triple travel due to mismatch at both the source and the evaluation board. Here the signal from the source reaches the evaluation board and mismatch causes a reflection. When that reflection reaches the source mismatch, it causes a new reflection, which travels back to the evaluation board, adding to the original signal incident at the board. The resultant voltage varies with both cable length and frequency dependence on the relative phase of the initial and reflected signals. Placing the 3 dB pad at the input of the board improves the match at the board and, thus, reduces the sensitivity to mismatches at the source. When such precautions are taken, measurements are less sensitive to cable length and other fixture issues. In an actual application when the distance between ADL5501 and source is short and well defined, this 3 dB attenuator is not needed. TO EDGE CONNECTOR C1 100pF VPOS C3 (OPEN) 2 C2 0.1F 1 ADL5501 VPOS FLTR RFIN VRMS ENBL COMM 6 R3 0 R5 (OPEN) C4 100nF VPOS SW1 R1 (OPEN) ENBL 06056-056 VRMS R2 (OPEN) 5 RFIN 3 4 R4 49.9 TO EDGE CONNECTOR Figure 56. Evaluation Board Schematic Table 5. Evaluation Board Configuration Options Component VPOS, GND C1, C2 C3 R2, R3, C4 Description Ground and Supply Vector Pins. Power Supply Decoupling. The nominal supply decoupling of 100 pF and 0.1 F. Filter Capacitor. The internal averaging capacitor can be augmented by placing additional capacitance in C3. Output Filtering. The combination of the internal 100 output resistance and C4 produce a low-pass filter to reduce output ripple. The output can also be scaled down using the resistor divider pads, R3 and R2. In addition, resistors and capacitors can be placed in C4 and R2 to load test VRMS. Device Enable. When the switch is set toward the SW1 label, the ENBL pin is connected to VPOS and the ADL5501 is in operating mode. In the opposite switch position, the ENBL pin is grounded (through the 49.9 resistor), putting the device in power-down mode. While in this switch position, the ENBL pin can be driven by a signal generator via the SMA labeled ENBL. In this case, R4 serves as a termination resistor for generators requiring a 50 match. Alternate Interface. R1and R5 allow for VRMS and ENBL to be accessible from the edge connector, which is used only for characterization. Default Condition Not Applicable C1 = 100 pF (Size 0402) C2 = 0.1 F (Size 0402) C3 = Open (Size 0402) R2 = Open (Size 0402) R3 = 0 (Size 0402) C4 = 100 nF (Size 0402) R4 = 49.9 (Size 0402) SW1 = toward SW1 label R4, SW1 R1, R5 R1 = Open (Size 0402) R5 = Open (Size 0402) Rev. 0 | Page 23 of 28 ADL5501 06056-057 Figure 57. Layout of Component Side Figure 59. Silkscreen of Component Side 06056-058 Figure 58. Layout of Circuit Side Figure 60. Silkscreen of Circuit Side Rev. 0 | Page 24 of 28 06056-060 06056-059 ADL5501 OUTLINE DIMENSIONS 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 PIN 1 1.30 BSC 1.00 0.90 0.70 6 1 5 2 4 3 0.65 BSC 1.10 0.80 0.40 0.10 0.46 0.36 0.26 0.10 MAX 0.30 0.15 0.10 COPLANARITY SEATING PLANE 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 61. 6-Lead Thin Shrink Small Outline Transistor Package [SC-70] (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model ADL5501AKSZ-R7 1 ADL5501AKSZ-R21 ADL5501-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C Package Description 6-Lead SC-70, 7" Tape and Reel 6-Lead SC-70, 7" Tape and Reel Evaluation Board Package Option KS-6 KS-6 Branding Q0Z Q0Z Ordering Quantity 3,000 250 Z = Pb-free part. Rev. 0 | Page 25 of 28 ADL5501 NOTES Rev. 0 | Page 26 of 28 ADL5501 NOTES Rev. 0 | Page 27 of 28 ADL5501 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06056-0-9/06(0) Rev. 0 | Page 28 of 28 |
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